Minimization of Total Harmonic Distortion of A Single Phase Inverter

Abstract

An approach of reducing the harmonics contained in the output of a single phase half bridge inverter has been depicted in this paper. The reason behind it is to improve the Total Harmonic Distortion (THD). RLC load is used instead of RL load so that capacitor has an impact on the output response which blocks the harmonics and undeniably passes almost sinusoidal output at the output terminal and it is certainly true that THD has been improved to a great extent. An illustration of Fourier Transform has been provided in this paper with a view to perceiving both the fundamental and harmonics component precisely. It has been found from simulation that the Total Harmonic Distortion (THD) with RL load is 44.052% that can be mitigated to only 4.12% by changing the prevalent load to RLC in which capacitor is connected in series with resistor and inductor.